A solid state drive (SSD) is a data storage device that utilizes solid-state memory to retain data in nonvolatile memory chips. NAND-based flash memories are widely used as the solid-state memory storage in SSDs due to their compactness, low power consumption, low cost, high data throughput and reliability. SSDs commonly employ several NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer.
While NAND-based flash memories are reliable, they are not inherently error-free and often rely on error correction coding (ECC) to correct raw bit errors in the stored data. Additionally, the bit error rate (BER) of the flash memory changes over the lifetime of the device. It is well known that NAND flash memory program/erase (PE) cycling gradually degrades the storage reliability of the memory device and stronger ECC techniques may be necessary over the lifetime of the device to ensure the data integrity. The lifetime of a flash block may be defined as the maximum number of P/E cycles after which the ECC in the SSD controller can no longer ensure the required storage reliability within a specific guaranteed data storage time. The gradual wear-out of the flash memory, as a result of the P/E cycling, undesirably diminishes the memory cell noise margin and increases the raw bit error rate (RBER) of the device.
One commonly employed error correction code for nonvolatile memory storage modules, such as SSDs, is the low-density parity-check (LDPC) code. An LDPC code is a linear error correcting code having a parity check matrix with a small number of nonzero elements in each row and column. Soft-decision message passing algorithms are known in the art for decoding data encoded with LDPC error correction codes, such as the sum-product algorithm (SPA) and the min-sum algorithm. These soft-decision message passing algorithms are iterative in nature and attempt to decode the encoded data by assigning probability metrics to each bit in an encoded code word. The probability metrics indicate a reliability of each bit, that is, how likely it is that the bit read from the memory is not in error. These probability metrics are commonly referred to log likelihood ratios (LLRs) in the case of LDPC decoding. These LLRs values are often stored in LLR look-up tables, which are accessible by the NAND flash controller.
NAND-based flash storage suffers from low endurance as each flash memory cell can tolerate only a limited number of program/erase (P/E) cycles. Due to the program/erase wear-out of the flash memory, the bit error rate (BER) of the memory device typically increases during its lifetime and as such, more error correction coding will be needed to guarantee the integrity of the stored data as the devices ages. It follows that the threshold voltage distribution and associated log likelihood ratios (LLRs) of the flash memory device also change over the lifetime of the device, as the LLR values are measures of the reliability of the data read from the memory storage.
To read the LDPC encoded data from the memory storage, a set of reference voltages are selected based upon the number of reads required and the number of bits used to represent the LLR value. The set of reference voltages selected determines the LLR values selected from the LLR look-up table. The accuracy of the LLR values are affected by the selection of the reference voltages used to read the memory storage. The selection of reference voltages that do not accurately represent the threshold voltage distribution of the memory storage result in the introduction or errors into the approximation of the LLR values which negatively impacts the LDPC performance. As such, it is important to select the best set of reference voltages to be used to read the LDPC encoded data from the memory module.
Accordingly, what is needed in the art is an improved system and method for decoding LDPC encoded data, wherein the best set of reference voltages are identified and used to read the LDPC encoded data and to extract the LLR values from the LLR look-up table prior to decoding of the data.